Digital Signal Processing Device

ABSTRACT

A digital signal processor includes K first electronic circuits. The first inputs receive K groups of G successive coefficients of a polynomial. The polynomial are of degree N with N+1 coefficients, where K is a sub-multiple of N+1 greater than or equal to two and G is equal to (N+1)/K. The first electronic circuits are configured to simultaneously implement K respective Homer methods and deliver K output results. A second electronic circuit includes a first input configured to successively receive the output results of the first electronic circuits starting with the output result of the first electronic circuit having processed the highest rank coefficient of the coefficients. A second input is configured to receive a variable X and the second electronic circuit is configured to implement a Homer method and deliver a value of the polynomial for the variable X on the output of the second electronic circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to French Application No. 2105332, filed on May 21, 2021, which application is hereby incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates generally to the field of circuits for signal processing and, in particular embodiments, to electronic circuits for the evaluation of polynomials.

BACKGROUND

The Homer algorithm, also called the Ruffini-Horner algorithm, allows evaluating polynomials, that is, calculating a value of a polynomial for a numerical value of its variable.

Conventionally, a processing circuit for the Homer algorithm comprises a circuit dedicated to the implementation of an elementary operation repeated during several iterations.

The dedicated circuit typically comprises a first input to successively receive all coefficients of the polynomial and a second input to always receive the same numerical value of the variable.

The dedicated circuit is configured to implement the elementary operation which provides for successively adding each new coefficient of the polynomial to a result of a previous iteration then multiplying a result of the addition by the numerical value of the variable at each iteration.

This dedicated circuit evaluates a polynomial in a large number of iterations, where the greater the number of iterations is, the greater the degree of the polynomial. A calculation time for the evaluation of the polynomial by the circuit is mainly dependent on the degree of the polynomial.

Such a dedicated circuit has the drawback of being relatively slow, particularly if the degree of the polynomial is high.

There is therefore a need for an electronic device allowing accelerating the evaluation of polynomials.

SUMMARY

According to one aspect, a device for determining the value of a polynomial of variable X is proposed, the polynomial being of degree N with N+1 coefficients.

The device comprises K first electronic circuits respectively having K first inputs respectively intended to receive K groups of G successive coefficients of the polynomial, K being a sub-multiple of (N+) greater than or equal to two, G being equal to (N+1)/K.

This polynomial of degree N, with (N+1) multiple of K, can be an initial polynomial for which it is desired to determine the value if this initial polynomial is actually of degree N, or else the initial polynomial of degree N0 supplemented with terms of higher degrees to reach the degree N, but affected by zero coefficients, if (N0+1) is not a multiple of K.

The ranks of the coefficients within each group are mutually offset by K starting with the highest rank coefficient in said group.

The K ranks of the K coefficients simultaneously received on the K first inputs are mutually offset by one.

The first circuit comprises K second inputs intended to receive the variable X^(K).

The first circuit also comprises K outputs.

The K first circuits are configured to simultaneously implement K respective Homer methods and deliver K output results on the K outputs.

Furthermore, the device comprises a second electronic circuit having a first input for successively receiving the output results of the K first circuits, starting with the output result of the first circuit having processed the highest rank coefficient.

The second circuit also has a second input to receive the variable X.

The second circuit also comprises an output.

The second circuit is configured to implement the Horner method and deliver the value of said polynomial on the output thereof.

Thus, the first K circuits in combination with the second circuit allow evaluating a polynomial in a number of iterations less than the degree N of the polynomial.

In particular, the K first circuits allow simultaneously implementing the K Homer methods on sub-polynomials of the polynomial. More specifically, the polynomial of degree N is subdivided into K sub-polynomials of degree (N+1)/K−1. The K first circuits allow simultaneously obtaining K evaluation results of these K sub-polynomials.

This allows reducing the number of clock strokes required to calculate the evaluation of the polynomial. Indeed, the number of clock strokes is divided by a factor close to K.

The second circuit then allows completing the evaluation of the polynomial by implementing the Homer algorithm once again from the K results of evaluation of the sub-polynomials, which allows obtaining the value of the polynomial for the value of the variable X.

According to one embodiment, each first circuit comprises a first adder having a first input connected to the first input of the first corresponding circuit.

The first adder has an output connected to the output of the first corresponding circuit.

The output of the first adder is looped back onto a first input of a first multiplier.

The first multiplier has a second input connected to the second input of the first corresponding circuit.

The output of the first multiplier is connected to the second input of the first adder.

According to one embodiment, the second circuit comprises a second adder having a first input connected to the first input of the second circuit.

The second adder has an output connected to the output of the second circuit.

The output of the second adder is looped back onto a first input of a second multiplier.

The second multiplier has a second input connected to the second input of the second circuit.

The output of the second multiplier is connected to the second input of the second adder.

Thus, each of the K first circuits and the second circuit can have the same structure comprising a multiplier and an adder, which allows simplifying the design of the device and being able in certain cases, such as for example within a signal processing processor, to use one of the first circuits as a second circuit.

Thus, according to another aspect, a signal processing processor is proposed incorporating the device as defined above, wherein the second circuit is one of the K first circuits.

Thus, such a processor allows removing a silicon surface dedicated to the second circuit by reusing one of the K first circuits to perform the calculations of the second circuit.

According to yet another aspect, a servo-control system is proposed, comprising a servo-control loop integrating a signal processing processor as defined above, connected to an electric motor.

Thus, the servo-control system benefits from the speed of calculation of the processor incorporating the device for the evaluation of trigonometric functions for example, which allows improving the accuracy of the servo-control loop.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and features will become apparent on examining the detailed description of embodiments and implementations, which are in no way limiting, and of the appended drawings in which:

FIG. 1 illustrates a device, in accordance with some embodiments;

FIG. 2 illustrates a digital signal processor, in accordance with some embodiments;

FIG. 3 illustrates a digital signal processor, in accordance with some other embodiments; and

FIG. 4 illustrates a servo-control system, in accordance with some other embodiments.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 1 schematically illustrates a device DIS comprising K first circuits C1_K1, C1_K2 (herein K=2) in parallel, a second circuit C2, and a controller MC, for example made in the form of a logic circuit.

The device DIS comprises GEN_CLK clock generator configured to generate a clock signal CLK clocking the first two circuits C1_K1, C1_K2, the second circuit C2 and the controller MC.

The device DIS comprises in relation to the first circuits C1_K1, C1_K2, a first input register RE1_K1, a second input register RE1_K2, a first output register RS_K1, a second output register RS_K2, and a first shared register RX_C1.

The device DIS also comprises, in relation to the second circuit C2, a third input register RE1_C2, a third output register RS_C2, and a second shared register RX_C2.

The device DIS is configured to evaluate the value of a polynomial of degree N and variable X, for a value of the variable X.

In the illustrated example, the polynomial to be evaluated is a polynomial of degree three (N=3) having a general form of the type P(X)=a₀+a₁X+a₂X²+a₃X³.

This polynomial therefore comprises four coefficients (N+1=4) which are distinguished by their ranks. The index of a coefficient which is equal to the degree of the variable with which it is associated is called “rank of a coefficient”.

For the sake of simplicity and brevity, the polynomial selected in the example of FIG. 1 is of degree three, nevertheless the greater the degree N of the selected polynomial, the more advantageous the device DIS is compared to other devices.

Some coefficients of the polynomial can be zero.

The first two circuits C1_K1, C1_K2 are configured to simultaneously implement two Horner methods for two sub-polynomials of variable X² so as to deliver two output results corresponding to the evaluation values of the two sub-polynomials for the value of the variable X².

Each of the sub-polynomials comprises a group of G (G=(N+1)/K) coefficients of the polynomial. Within a group of coefficients of a sub-polynomial, the coefficients have ranks which are mutually offset by two. Each group comprises herein two coefficients (G=2). Each sub-polynomial is herein of degree one for the variable X².

The first circuit C1_K1, on the left in the Figure, is configured to evaluate a sub-polynomia A(t)=a₀+a₂t for the variable t=X², i.e. to deliver the result of the evaluation of A(X²).

The first circuit C1_K2, on the right in the Figure, is configured to evaluate a sub-polynomial B(t)=a₁+a₃t for the variable t=X², i.e. to deliver the result of the evaluation of B(X²).

To this end, the first left circuit C1_K1 has a first input E1_K1 intended to receive a first group of two coefficients a₀, a₂ of the polynomial P(X), a second input E2_K1 intended to receive the value of the variable X², and an output S_K1 on which the result of the evaluation of the sub-polynomial A(X²) is intended to be delivered.

In parallel, the first right circuit C1_K2 has a first input E1_K2 intended to receive a second group of two coefficients a₁, a₃ of the polynomial P(X), a second input E2_K2 intended to receive the value of the variable X², and an output S_K2 on which the result of the evaluation of the second sub-polynomial B(X²) is intended to be delivered.

The first input register RE1_K1 is connected to the first input E1_K1 of the first left circuit C1_K1 and the second input register RE1_K2 is connected to the first input E1_K2 of the first right circuit C1_K2.

The first output register RS_K1 is connected to the output S_K1 of the first left circuit C1_K1 and the second output register RS_K2 is connected to the output S_K2 of the first right circuit C1_K2.

The first shared register RX_C1 is connected to the second inputs E2_K1 and E2_K2 of the first two circuits C1_K1, C1_K2.

Each first circuit C1_K2, C1_K2, comprises a first adder AK_1, AK_2 and a first multiplier M_K1, M_K2.

Each first adder A_K1, AK2 has a first input E1A_1, E1A_K2 connected to the first input E1_K1, E1_K2 of the first corresponding circuit.

Each first adder A_K1, AK2 comprises an output SA_K1, SA_K2 connected to the output S_K1, S_K2 of the first corresponding circuit.

This output S_K1, S_K2 is looped back onto a first input E1M_K1, E1M_K2 of one of the first multipliers M_K1, M_K2.

Each first multiplier M_K1, M_K2 has a second input E2M_K1, E2M_K2 connected to the second input E2_K1, E2_K2 of the first corresponding circuit.

Each first multiplier M_K1, M_K2 comprises an output SM_K1, SM_K2 connected to the second input E2A_K1, E2A_K2 of the first adder A_K1, A_K2.

The evaluation of the sub-polynomials by the first circuits C1_K1, C2_K2 is simultaneously performed by successive iterations.

The term “iteration” means a step of calculating the first circuits C1_K1, C1_K2 comprising a number of cycles of the clock signal CLK sufficient to obtain a new result on all outputs S_K1, S_K2 of the first circuits C1_K1, C2_K2. For example, all iterations can comprise the same number of cycles of the clock signal CLK. Each iteration can, for example, comprise a single cycle of the clock signal CLK.

During the evaluation of the sub-polynomials, the first inputs of the first adders A_K1, A_K2 simultaneously receive the values of the coefficients of the sub-polynomials by decreasing ranks at each iteration, and the second inputs of the first multipliers M_K1, M_K2 receive the variable X^(K), herein X².

All values of the coefficients of the polynomial to be evaluated are known in advance and for example stored in a memory. If for a given rank the value of a coefficient is zero, then a zero value is received at the input of the first corresponding adder A_K1. or A_K2.

The operation of the device of FIG. 1 will be described now.

The first inputs of the first adders A_K1, A_K2, and the inputs of the first multipliers M_K1, M_K2 are initialized to zero.

A first iteration then begins on a first edge of the clock signal CLK.

The controller MC loads the coefficient a₂ in the first input register RE1_K1, the coefficient a₃ in the second input register RE1_K2, and the value of the variable X² in the first shared register RX_C1.

The first input E1_K1 of the first left circuit C1_K1 receives the coefficient a₂, the first input E1_K1. of the first right circuit C1_K2 receives the coefficient a₃, and the second inputs E2_K1, E2_K2 of the first corresponding circuits C1_K1, C1_K2 receive the variable X².

The outputs SM_K1, SM K2 of the first multipliers M_K1, M_K2 give zero and the outputs SA_K1, SA_K2 of the first adders A_K1, A_K2 give respectively the value of the coefficient a₂ and the value of the coefficient a₃.

At the end of the first iteration, the first adders A_K1, A_K2 deliver intermediate output results from the first circuits C1_K1, C1_K2. The value of the coefficient a₂ is delivered on the output S_K1 of the first left circuit C1_K1 and the value of the coefficient a₃ is delivered on the output S_K2 of the first right circuit C1_K2.

A second iteration begins on a second edge of the clock signal CLK, the controller MC loads the coefficient a₀ into the first input register RE1_K1, the coefficient a₁ into the second input register RE1_K2, and the value of the variable X² in the first shared register RX_C1.

The first input E1_K1. of the first left circuit C1_K1 receives the coefficient α₀, the first input E1_K1. of the first right circuit C1_K2 receives the coefficient a₁ and the second inputs E2_K1, E2_K2 of the first corresponding circuits C1_K1, C1_K2 receive the variable X².

The first inputs E1M_K1, E1M_K1. of the first multipliers M_K1, M_K2 receive the intermediate output results of the corresponding first circuits C1_K1, C1_K2.

Thus the first input E1M_K1 of the first multiplier M_K1 of the first left circuit C1_K1 receives the value a₂ and the first input E1M_K1 of the first multiplier M_K1 of the first circuit on the right C1_K2 receives the value a₃.

The outputs SM_K1, SM_K2 of the first multipliers M_K1, M_K2 give respectively the value a₂X² and the value a₃X², and the outputs SA_K1, SA_K2 of the first adders A_K1, A_K2 give respectively the value A(X²) and the value B(X²).

At the end of the second iteration, the first adders A_K1, A_K2 deliver the output results of the first circuits C1_K, C2_K on the corresponding outputs S_K1, S_K2. The first left circuit C1_K1 delivers the value of A(X²) on the associated output S_K1 and the first right circuit C1_K2 delivers the value of B(X²) on the associated output S_K2.

The controller MC is configured to transfer the output results from the output registers of the first circuits C1_K1, C1_K2 to the input register RE1_C2 of the second circuit C2.

The second circuit C2 is configured to process the two output results A(X²), B(X²) of the first circuits C1_K1, C1_K2 so as to deliver the value of the polynomial P(X).

In particular, the second circuit C2 is configured to implement a Homer method to evaluate a reformulation of the expression of the initial polynomial by noting that P(X)=A(X²)+XB(X²).

To this end, the second circuit C2 has a first input E1_C2 to successively receive the output results of the first two circuits, starting with the output result B(X²) of the first right circuit C1_K2 (which processed the highest rank coefficient a₃) then by the output result A (X²) of the first left circuit C1_K1.

The second circuit C2 also comprises a second input E2_C2 to receive the variable X, and an output S_C2 to deliver the value of the polynomial.

The third input register RE1_C2 is connected to the first input E1_C2 of the second circuit C2.

The third output register RS_C2 is connected to the output S_C2 of the second circuit C2.

The second shared register RX_C2 is connected to the second input E2_K1 of the second circuit C2.

The second circuit C2 further comprises a second adder A_C2 having a first input E1A_C2 connected to the first input E1_C2 of the second circuit.

The second adder A_C2 comprises an output SA_C2 connected to the output S_C2 of the second circuit.

The output of the second adder A_C2 is looped back onto a first input E1M_C2 of a second multiplier M_C2.

The second multiplier M_C2 has a second input E2M_C2 connected to the second input E2_C2 of the second circuit C2.

An output SA_C2 of the second multiplier M_C2 is connected to a second input E2A_C2 of the second adder A_C2.

The second circuit C2 delivers the value of the polynomial in two successive iterations after the second iteration of the first circuits C1_K1, C2_K2.

The first inputs of the second adder A_C2 and the inputs of the second multiplier M_C2 are initialized to zero.

A third iteration begins on a third edge of the clock signal CLK, the controller MC loads the output result B(X²) of the first right circuit C1_K2 into the third input register RE1_C2, and the value of the variable X in the second shared register RX_C2.

The first input E1_C2 of the second circuit C2 receives the output result B(X²) of the first right circuit C1_K2, and the second input E2_C2 of the second circuit C2 receives the variable X.

At the end of the third iteration, the second adder A_C2 delivers the value B(X²) on the output S_C2 of the second circuit C2.

A fourth iteration begins on a fourth edge of the clock signal CLK, the controller MC loads the output result A(X²) of the first left circuit C1_K1 into the third input register RE1_C2, and the value of the variable X in the second shared register RX_C2.

The first input E1_C2 of the second circuit C2 receives the output result A(X²) from the first left circuit and the second input E2_C2 of the second circuit C2 receives the variable X.

At the end of the fourth iteration, the second adder A_C2 delivers a value of the polynomial P(X)=A(X²)+XB(X²) on the output S_C2 of the second circuit C2.

Although the first circuits C1_K1, C1_K2 and the second circuit C2 have been described above as being distinct circuits, nevertheless it is advantageously possible to use one of the first circuits to carry out the functions of the second circuit C2, for example when the device DIS is incorporated into a signal processing processor DSP (FIG. 2).

Indeed, the second circuit C2 advantageously has a structure similar to the structure of each first circuit C1_K1, C1_K2.

In addition, as previously described above, the iterations implemented by the second circuit C2 to obtain the value of the polynomial are carried out only after the end of the iterations implemented by the first circuits C1 to obtain the output results.

When the second circuit C2 is one of the first circuits C1_K1, C1_K2, the controller MC are configured to handle contents stored in the output registers of the first circuits C1_K1, C1_K2, such that during the third and fourth iterations the output results of the first circuits are fed back into the first input register connected to the first input of the first circuit acting as a second circuit C2.

Likewise, when the second circuit C2 is one of the first circuits, the first shared register RX_C1 is the second shared register RX_C2.

The first shared register then stores the value of the variable X² during the first and second iteration and stores the variable X during the third and fourth iteration.

FIG. 3 schematically illustrates a signal processing processor DSP comprising a device DIS having herein four first circuits C1_K1, C1_K2, C1_K3, C1_K4 in parallel and a second circuit C2.

Again, although the second circuit C2 has been represented separately, it is advantageously functionally formed by one of the first four circuits C1_Ki.

The signal processing processor DSP in FIG. 3 allows quickly evaluating high degree polynomials.

Indeed, the greater the number K of first circuits, the more a high degree polynomial is subdivided into a large number K of sub-polynomials, which is advantageous in order to accelerate the calculation of the value of the polynomial P.

In the example of FIG. 3, the polynomial to be evaluated is a polynomial of degree eleven (N=11) of a general form of the type P(X)=a₀+a₁X+a₂X²+a₃X³+a₄X⁴+a₅X⁵+a₆X⁶+a₇X⁷+a₈X⁸+a₉X⁹+a₁₀X¹⁰+a₁₁X¹¹. This polynomial therefore comprises twelve coefficients (N+1=12).

The first four circuits C1_K1, C1_K2, C1_K3, C1_K4 are configured to simultaneously implement four Homer methods for four sub-polynomials and deliver four evaluation output results of these four sub-polynomials.

The first circuit C1_K1, on the left in the Figure, is configured to evaluate a sub-polynomial A(t)=a₀+a₄t+a₈t² for the variable t=X⁴, i.e. to deliver the result of the evaluation of A(X⁴).

The first circuit C1_K2, in the middle on the left in the Figure, is configured to evaluate a sub-polynomial B (t)=a₁+a₅t+a₉t² for the variable t=X⁴, i.e. to deliver the result of the evaluation of B (X⁴).

The first circuit C1_K3, in the middle on the right in the Figure, is configured to evaluate a sub-polynomial C(t)=a₂+a₆t+a₁₀t² for the variable t=X⁴, i.e. to deliver the result of the evaluation of C(X⁴).

The first circuit C1_K4, on the right in the Figure, is configured to evaluate a sub-polynomial D(t)=a₃+a₇t+a₁₁t² for the variable t=X⁴, i.e. to deliver the result of the evaluation of D(X⁴).

The second circuit C2 is configured to process the output results A(X⁴), B(X⁴), C(X⁴), D(X⁴) of the first circuits C1_K1, C1_K2, C1_K3, C1_K4 so as to deliver the value of the polynomial P(X).

In particular, the second circuit C2 is configured to implement a Homer method to evaluate a reformulation of the expression of the initial polynomial by noting that P(X)=A(X⁴)+XB(X⁴)+X²C(X⁴)+X³C(X⁴).

The device DIS comprises for each of the first circuits a first input register RE1_K1, RE1_K2, RE1_K3, RE1_K4 intended to successively store the coefficients of the polynomial P(X) and an output register RS_K1, RS_K2, RS_K3, RS_K4 to store the output results A(X⁴), B(X⁴), C(X⁴), D(X⁴).

Each of the first circuits comprises a second input connected with the same shared register RX_C1 in particular adapted to store the value of the variable X^(K), herein X⁴.

The second circuit C2 comprises a first input connected to a third input register RE1_C2 intended to successively store the output results D(X⁴), C(X⁴), B(X⁴), A(X⁴)d in the reverse order of the first circuits, that is to say starting with the output result D(X⁴) of the first right circuit C1_K4 which processed the highest rank coefficient a₁₁.

The second circuit C2 comprises a second input connected to a fourth input register RX_C2 intended to store the value of the variable X.

The operation of the first circuits C1_K1, C1_K2, C1_K3, C1_K4 is analogous to the operation described in relation to FIG. 1. Likewise, the operation of the second circuit C2 is analogous to the operation described in relation to FIG. 1.

At the end of the iterative calculation performed by the device DIS, the value of the polynomial P(X) is contained in the output register RS_C2.

FIG. 4 illustrates a servo-control system SYS comprising a servo-control loop integrating a control unit UC, for example a microcontroller such as that marketed by the company STMicroelectronics under the reference STM32, connected to an electric motor M.

The control unit UC comprises a processing unit CPU and a signal processing processor DSP incorporating the device DIS described above to implement a servo-control of the electric motor M.

For the servo-control of the motor, it may for example be advantageous to evaluate a sine or cosine function, in particular in the case of a servo-control of the angle of rotation of the electric motor M.

A polynomial approximating a sine function is for example sin(X)≈P(X)=X(1+X²(s₁+X²(s₂+X²(s₃+X²(s₄+X²(s₅+s₆X²)))))).

A polynomial approximating a cosine function is for example cos(X)≈P(X)=1+X²(c₁+X²(c₂+X²(c₃+X²(c₄+X²(c₅+c₆X²))))).

Thus, it is therefore advantageous for the servo-control loop to implement the device DIS as described above in order to quickly evaluate the trigonometric function whose value is sought. 

What is claimed is:
 1. A digital signal processor comprising: K first electronic circuits comprising K first inputs, K second inputs, and K outputs, wherein the first inputs are configured to receive K groups of G successive coefficients of a polynomial, the polynomial being of degree N with N+1 coefficients, K being a sub-multiple of N+1 greater than or equal to two, G being equal to (N+1)/K, ranks of the coefficients within each group being mutually offset by K starting with the highest rank coefficient in said group, the ranks of the coefficients received simultaneously on the first inputs being mutually offset by one, wherein the second inputs are respectively configured to receive a variable X^(K), and wherein the first electronic circuits are configured to simultaneously implement K respective Homer methods and deliver K output results on the outputs; and a second electronic circuit comprising a first input, a second input, and an output, wherein the first input is configured to successively receive the output results of the first electronic circuits starting with the output result of the first electronic circuit having processed the highest rank coefficient of the coefficients, wherein the second input is configured to receive a variable X, wherein the second electronic circuit is configured to implement a Homer method and deliver a value of the polynomial for the variable X on the output of the second electronic circuit.
 2. The digital signal processor of claim 1, wherein each first corresponding circuit of the first electronic circuits comprises: a first multiplier comprising a first input, a second input, and an output, the first input of the first multiplier connected to the second input of the first corresponding circuit; and a first adder comprising a first input, a second input, and an output, the first input of the first adder connected to the first input of the first corresponding circuit, the second input of the first adder connected to the output of the first multiplier, the output of the first adder connected to the output of the first corresponding circuit and looped back onto the second input of the first multiplier.
 3. The digital signal processor of claim 2, wherein the second electronic circuit comprises: a second multiplier comprising a first input, a second input, and an output, the first input of the second multiplier connected to the second input of the second electronic circuit; and a second adder comprising a first input, a second input, and an output, the first input of the second adder connected to the first input of the second electronic circuit, the second input of the second adder connected to the output of the second multiplier, the output of the second adder connected to the output of the second electronic circuit and looped back onto the second input of the second multiplier.
 4. The digital signal processor of claim 1, wherein the second electronic circuit is one of the first electronic circuits.
 5. The digital signal processor of claim 1, wherein the second electronic circuit is different from each of the first electronic circuits.
 6. A servo-control system comprising: a servo-control loop integrating the digital signal processor of claim 1; and an electric motor connected to the servo-control loop.
 7. The servo-control system of claim 6, wherein the servo-control loop is configured to evaluate a polynomial approximation of a sine function, and to control an angle of rotation of the electric motor.
 8. The digital signal processor of claim 1, wherein K is two.
 9. The digital signal processor of claim 1, wherein K is four.
 10. A digital signal processor comprising: a first circuit configured to receive a first sub-polynomial of an input polynomial, evaluate the first sub-polynomial with a first Homer method, and output a first intermediate result of evaluating the first sub-polynomial; a second circuit configured to receive a second sub-polynomial of the input polynomial, evaluate the second sub-polynomial with a second Homer method, and output a second intermediate result of evaluating the second sub-polynomial, wherein the first Homer method and the second Homer method are simultaneously implemented; and a third circuit configured to receive the first intermediate result and the second intermediate result, evaluate the first intermediate result and the second intermediate result with a third Homer method to produce a final result of evaluating the input polynomial, and output the final result.
 11. The digital signal processor of claim 10, wherein the final result is a result of evaluating the input polynomial for a value, and the first sub-polynomial and the second sub-polynomial are of degree one for the value squared.
 12. The digital signal processor of claim 10, wherein the first circuit is configured to receive the first sub-polynomial by receiving first coefficients in a first input register for the first circuit, the second circuit is configured to receive the second sub-polynomial by receiving second coefficients in a second input register for the second circuit, and the first coefficients and the second coefficients have ranks that are mutually offset by two.
 13. The digital signal processor of claim 12 further comprising: a control circuit configured to load the first coefficients in the first input register during a first iteration, load the second coefficients in the second input register during a second iteration, and load the first intermediate result and the second intermediate result in a third input register for the third circuit during a third iteration.
 14. The digital signal processor of claim 10, wherein the first circuit comprises a first adder and a first multiplier, and the second circuit comprises a second adder and a second multiplier.
 15. The digital signal processor of claim 14, wherein the third circuit comprises a third adder and a third multiplier.
 16. The digital signal processor of claim 14, wherein the third circuit comprises the second adder and the second multiplier. 